| With the development of digital signal processor technology, more and more analog signal processing are replaced by digital signal processing. But in the nature and real world. the signals are almost analog signals which variety continual. They need analog-to-digital converter to transform the analog signal into digital signal.Compare with foreign company, the research of A/D converter in our country is still poor. When about to the chips which can provided to client numerous are seldom. Domestic research was mainly concentrated in the flash and pipelined ADC, who have the characteristic of high-speed and low-precision. The structure for low power consumption and small die size of the analog-to-digital converter are few studied. Therefore, this paper research and design an ADC who has the feature of low power consumption, medium accuracy, small size. This design make up the deficiencies in this regard.Using the top-down design method, a10bit successive approximation register ADC used in fingerprint identify is designed in this thesis. It has a power voltage of3.3V and converter rate of300ksps. The main works of this thesis are as follow:(1) Analysis the project design requirements, successive approximation ADC as a target system. Then the technical difficulties faced in this design are proposed.(2) Sample and hold circuit utilizes dummy switch technique to reduce the deviation voltage caused by switch charge inject. Using CMOS complementary switches, it not only reduces the conduction resistance of the switch, but also the resistance nonlinear caused by input signal. This can make the sampling time shorter.(3) A unique configuration of charge scale and voltage scale is adopted in D/A converter implementation, which avoid the large area and mismatch caused by big capacitors or resistors and minish the linear error of circuit. Because of the use of charge scaling and voltage scaling, this extends the resolution of a parallel D/A converter as well as reduces the chip area greatly.(4) For the design of comparator, the architecture of preamplifiers followed by a dynamic latch is employed. The preamplifier has the characteristics of low-gain and high-bandwidth. The dynamic latch has the characteristics of fast response, and can reduce power consumption effectively. So this design can satisfies the requirement of high speed and the low power.In this paper, the SAR ADC is designed by using AMS0.35um mixed CMOS technology. With the software of Cadence IC design kit, the circuit and layout design are accomplished. The whole circuit is post simulated at system level. The results show that, its SFDR achieves73.06dB at300ksps, ENOB is9.77bit. The whole ADC’s power consumption is1.75mW. The area of chip is680um×350um. From the results, the design is able to complete the analog-to-digital conversion correctly, and achieve the requirements of moderate accuracy, low power consumption, small size. |
