Study And Design Of RLS Digital Calibration For A/D Converter

With the continuous development of the digital electronics industry, ADCs calibrationtechnology gradually becomes a hot topic. In recent years, the digital calibration for ADCsbased on recursive least squares (RLS, Recursive Least Square) algorithm has become ahotspot on the RLS algorithm due to fast convergence, strong tracking ability. However, theRLS algorithm in the ADC’s calibrating application is still limited to its local error. There forin this thesis, RLS digital calibration architecture was studied for correcting high-precisionbut inaccurate ADC’s errors.Firstly, the basic principle of RLS algorithm was analyzed. The structures and errors ofdifferent ADCs was discussed. Then, RLS algorithm’s performance was simulated in Matlab.And the Simulink model of the calibration system for the ADC was developed. Thesimulation results show that using RLS adaptive algorithm calibration, ADCs ENOB can beimproved from10.87bit to13bit, SNR can be improved from67.20dB SNR to80.03dB,SFDR can be improved from72.56dB to88.25dB; RLS filter can effectively filter outharmonic signal and the accuracy of the ADC is improved.In order to verify the validity of RLS algorithm, a hardware implement scheme isdesigned for the RLS algorithm’s performance tests. This scheme is realized by floating DSP.A sixteenth order RLS adaptive filter which was designed in C language on the CCSenvironment was downloaded to the DSP TMS320F28335. Hardware verification resultsshow that through the RLS algorithm adaptive filter, Gaussian white noise and harmonic ofsinusoidal signals can be filtered. Signal’s SNR can be improved from11.31dB to20.88dB.The simulation results show that the RLS adaptive digital filter is valid and has a betterfiltering.