Research And Implementation Of The Analog Circuit In The DVI Receiver

Since the DVI1.0Standard was released by the DDWG working group in1999,the emergence of Digital Video Interface (DVI) technology has spurred a newrevolution of the whole video interface technology and market. As an excellent videointerface technology, DVI is rapidly supported by the worldwide industry andmanufacturers. Nowadays, the DVI technology is widely used in the whole field ofvideo due to its rapid development in the past14years.The DVI technology adopts the transport protocol of TMDS and supports thedisplay standards from VGA to UXGA. As for the single TMDS, its link clockfrequency and the data rate can be25MHz~165MHz and250Mbps~1.65Gbp,respectively. In this paper, Based on DVI1.0standard, TMDS data transmissionmode, TMDS link structure and the DVI interface system structure, I proposed thefunctional block diagram of the data flow in DVI receiver. This dissertation focuseson the functional analysis and analog circuit design of each module in the DVIreceiver. The related analog circuit module mainly includes three parts: High-speeddifferential receiver, the3X oversampling data recovery circuit and the12equalphase clock output charge pump phase-locked loop. The detail of the function andprinciple are analyzed, some optimization solutions and improvement ofconventional circuit are given. Such as Level conversion circuit, phase frequencydetector, charge pump, Voltage controlled oscillator, etc.The layout design of the circuit in this dissertation is realized by using the SMIC0.11μm hybrid process. Use Cadence Virtuoso tools to implement circuit design,Spingsoft of the Laker tools complete landscape design. The whole layout area is264*145μm2. Use Synopsys of the Hspice software to complete before the circuitsimulation and layout simulation. The circuit properties achieved from thepost-simulation can well satisfy the DVI1.0Standard. As in the VGA resolutionmode, the receiving clock frequency and data rate are25MHz and250Mbps,respectively. The PLL can be locked in3.6μs; the system can operate in stable modein5.3μs; the peak-to-peak value of the output clock jitter in a period is1.36%. As inthe UXGA resolution mode, the receiving clock frequency and data rate are165MHzand1.65Gbps, respectively. The PLL can be locked in2μs; the system can operate instable mode in4.5μs; the peak-to-peak value of the output clock jitter in a period is0.59%.