The Design Of High Speed A Low Jitter Fully Differential CMOS Phase Locked Loop

Phase locked loop(PLL) frequency synthesizer has been widly implemented in communication and microprocessor System, and it has become the required module in the VLSI along with the developmen of IC and SOC technology. Especially in the realm of wireless communication and high speed processor, the higher requirements for PLL circuit performance is proposed.Therefore, the PLL circuit performance on the high-speed condition is challenged currently.Based on the research for the PLL technology history and its current state, from the perspective of how it works, this thesis analyzes the mathematics model of PLL. The stability, the dynamic characteristics and the noise characteristics of the PLL are later analyzed. We get the priciples of choosing the parameters of the system loop, which lays the theoretical foundation for circuit designing and layout designing. After that, the advantages and disadvantages of the tradition circuit structures are analyzed, and new circuit structures are proposed. The next paragraph gives out all the main improvements.The first improvement is adopting a new PFD circuit structure, which can remove the dead zone without bringing the phenomena of missing clock edge by prolonging the delay time of the reset control signal. The second improvement is using resistors instead of the current source MOS-FFETs in the charge pump, which eliminates the impact of flicker noise. The third improvement is using a fully differential regulator but not a single for the VCO, which further reduces power supply noise impact on VCO. The last improvement is that the divider is construct of low speed D-flip-flop(DFF) and high speed DFF which is based on TSPC structure.The CPPLL is designed in SMIC 0.13?m 1P8M 1.2V mixed signal CMOS technology. The die size of the core IP is 400?m *400?m. When input reference frequency is 25MHz, output frequency is 2.5GHz, the locking time is less than 20?s, the power consumption is no more than 25mW, besides, the rms jitter of pre-simulation is 4.63 ps at 2.5GHz output frequency.