Research And Implementation Of Clock Mesh Automatic Synthesis

The traditional balance tree clock structure is becoming more and more incapableof meeting the anti-jamming, low skew requirements of the large scale highperformance synchronous digital circuits for it is vulnerable to process, voltage andtemperature variations. Mesh architecture offers high tolerance towards variation in theclock skew due to its high redundancy. However, such a redundancy comes at theexpense of mesh wire resources. Moreover, the mainstream EDA tools do not supportfully automatic non-tree clock structure synthesis so far which limits the wide use of theclock mesh.Based on the layout and timing analysis abilities of EDA tools, and by usinga set of effective algorithm, we realize full automation in synthesizing clock mesh andachieve the goal of minimizing wires length (power consumption) as much as possibleunder the target clock skew. The main contributions are as follows:We propose a new mesh size planning algorithm so as to reduce the powerconsumption due to the wire parasitic capacitance to the greatest extent on the premisethat the user specified clock skew is satisfied. Firstly, the design is partitioned into stripswhich will be sorted by the number of sinks inside each strip area. Then by traversingcalculation to decide the final mesh size for optimal grid line capacitance as well asmeeting the clock skew target.We propose a sink relocation method under the pure mesh and mesh with localtrees cases to optimize the stubs length. The timing slacks are considered in the formercase so as to minimize the negative impact on the timing while optimizing wire length(power) and clock skew.We propose a mesh trunk trim method based on the “driver window” model whichfurther reduces the unnecessary waste of routing resources, and this also reduces powerconsumption and the burden on the mesh driver level.We propose a mesh driver optimization method based on the "drive window"model. By estimating the load in the "window" and traversing bilinear interpolationcalculation to obtain the minimum size of the mesh driver for each “window”. Thatavoids excessing use of driver resources.We establish the user input mechanism similar to CTS which will synthesize andsimulate the clock mesh automatically according to certain main user specified clockperformance indicators such as clock skew and transition time. Finally, we create amenu GUI along with a custom command and both of them are embedded in thebackend EDA tool--IC Compiler which offers a great convenience to users.In a word, the results of benchmark circuits’ test show that the mesh wire length,buffer area, mesh power, clock skew and run time are better with propose method. Anexperiment on an additional project case shows that, compared with half automation algorithm of a previous related works, all indicators of the clock mesh, which issynthesized by fully automatic method of this thesis, are improved by at least more than20%. In particular, the buffer area is reduced by nearly87%. All those manifest thepracticality of the proposed clock mesh automatic synthesis process.