On Global Clock Mesh Synthesis And Optimization

With the rapid development of semiconductor technology, the characteristic dimension shrinks. 65nm and 45nm technology have become the mainstream, it's believed that 32nm and 22nn technology will be in the near future. But, as side effect of technology advancement, many factors have a great impact on clock quality. Clock design is now the key to the whole backend design. The traditional clock tree structure was no longer able to meet the challenging timing and power constraints. Clock mesh structure, on the other hand, due to its robustness to variances and small clock skew, it has been applied to high-speed chip design successfully, such as 600-MHZ Alpha, IBM G5 S/930, Power4, Power PC, and SUN Sparc V9. However, clock mesh is not applied widely, because of the lack of good EDA tool support.This dissertation presents a full automation synthesis and optimization framework of clock mesh, which includes six major steps as follows: mesh planning, stem placement, local routing, buffer insertion, verification and buffer relocation optimization. The detail algorithm on each step will be discussed, with the goal to meet the timing and power constraints. Also, we will summarize the general characteristic of clock mesh. The experiment results show that our clock mesh synthesis and optimization framework performances well on standard academic testcases, meeting the strict timing and power constraints.