The Design Of12-bit High-reliability Analog-to-digital Converter

With the development of digital signal processing technology andintegrated circuit manufacturing process, the performance of graphic, video,audio, wireless communications and other fields SOC chip is becoming moreand more powerful. Most of these chips, they use digital signals to completetheir tasks. As the design of digital circuits are becoming increasingly important,analog circuits on the SOC chip has gradually become a bottleneck affecting thechip’s performance.ADC, Analog to Digital Converter (ADC), which is applied to convert theanalog input to a digital code according to the certain rules, is the bridge thatconnects the real world analog signals to the electronic system digital signal s.This thesis chose one kind of architecture named pipelined ADC, its high-speedand high-precision can meet the initial requirements, and it could have a highpractical value in many aspects.The integrated circuit in this thesis is based on GSMC0.18μm CMOSprocess, and it is aimed to be integrated in the microcontroller chip, which willbe installed in smart house applications. The main work of this thesis includes:1. The entire ADC circuit system architecture is designed, and simulation foreach stage is completed. In order to improve the reliability of ADC circuits,each stage has been carefully adjusted;2. The function module design and simulation is completed, including: precisetwo-phase non-overlapping clock circuit design; voltage bias circuit design;switched capacitor sample and hold circuit design; high-speedpre-amplification latched comparator, high-performance operationalamplifier design; digital delay and calibration circuit design.The overall chip simulation results show that this ADC can operate well at40MSPS in12bits. The design of pipelined ADC meets the original goals.