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The Design Of 10-bit High-Speed Pipelined Analog-to-Digital Converter

Posted on:2008-03-23Degree:MasterType:Thesis
Country:ChinaCandidate:J Y SunFull Text:PDF
GTID:2178360242467045Subject:Physical Electronics
Abstract/Summary:PDF Full Text Request
As an interface circuit, Analog to Digital converter (ADC) is used to convert analog signals to digital signals with the certain rules. With the explosive development of communication and digital signal processing technology, the digital system has been becoming the main body pattern. An analog-to-digital converter, as an interface between analog signal and digital signal, especially is demanded in video and wireless communication field. At the same time, pipelined ADC has a good tradeoff between speed and dissipation, so it is widely used.In this dissertation, based on TSMC 0.25um CMOS technology, a low power 10 bits 40MS/s pipelined ADC is designed with the EDA tool of Cadence IC 5.0. Main work of this dissertation includes: by analyzing a great deal of literatures, 1.5 bits per stage structure is designed to obtain minimizing power dissipation in high speed pipelined ADC; design an accurate non-overlapping clock circuit to provide clock signal for the pipeline; design a bandgap voltage reference circuit and the bias circuit to provide precise voltage and current reference for the referred ADC; design a thermal-shutdown circuit to enhance the headroom of too high working temperature; make the sample-and-hold circuit as the input stage to reduce the noise effect; design a series of high speed low power dynamic comparators and low power high performance Miller opamps to improve the performance of system; Design a digital correction circuit to enhance the headroom of comparator offset. At the same time, a series of simulation and analysis are maked by the tool of SpectreS and Hspice. And a series of code desity and FFT analysis for system static and dynamic performance are maked by Matlab. At last, some layouts of the circuits are finished in this paper.The ADC consumes about 13.2 mW on a 2.5V supply, so it is a low power chip. The simulation results of the chip and the static and dynamic performance of the system show that the 10bit 40MS/s pipelined ADC designed in this dissertation has good performance, and also it is valuable in theoretics research and application.
Keywords/Search Tags:ADC, Pipeline, High-speed, Low-power
PDF Full Text Request
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