Research On Fundamental Theory And Key Technologies Of High-Speed High-Resolution Photonic Analog-to-Digital Convertor System

Photonic analog-to-digital converter(PADC)is an up-to-date signal processing technology,which is based on microwave photonics and traditional electronic analog-to-digital converters(EADC).Limited by the so-called “electronic bottleneck”,EADCs are no longer feasible in the face of rapidly increasing frequency and bandwidth in modern communication and radar systems.PADC technology utilizes high-speed and low-noise photonic pulse train as the sampling clock and develops electro-optical sampling via sampling gate with large analog input bandwidth.With all the advancements in speed,resolution and input bandwidth,PADC breaks through the “electronic bottleneck” effectively.Especially,in the PADC scheme consisted of a photonic front-end and an electronic back-end,the inherent advantages of photonic technology are combined with the convenience of electronic devices,which provides an ideal and practical solution for signal acquisition and processing in next-generation radar and communication systems.This dissertation is focused on high-speed high-resolution PADC technology based on active mode-locked laser(AMLL).Compared with other PADC techniques,this scheme makes full use of the speed advantage of AMLL,achieving an ultra-high sampling rates and ensuring highresolution digitization under low system complexity.Hence,this scheme is expected to become an optimal choice to achieve high-speed high-resolution PADC.The research contents of this dissertation include the theory and mathematical analysis of PADC system,the technology of high-speed and high-quality photonic sampling clock generation,the experimental implementation of high-speed high-resolution PADC system and the PADC performance limitation.The accomplished work and the achievements in this dissertation are summarized as follows:First,the mathematical model is established according to the physical essence of PADC.Both theoretical analysis and numerical simulation are developed for channel-interleaved PADC system based on high-speed AMLL.The working mechanism of each components in the system are studied,including photonic sampling clock generation,electro-optic sampling,multi-channel demultiplexing,photodetection,and electronic digitization.Based on the theoretical analysis of the PADC system,a performance evaluation method is derived and the design criteria of the PADC system is also given,which could become an effective guidance for experimental implementation.Second,an ultra-high-speed photonic sampling clock based on an AMLL is demonstrated via time-wavelength interleaving(TWI)scheme and the channel mismatch effect on the clock generation is analyzed.Theoretically,a mathematical model describing the clock generation mechanism is derived and a numerical simulation of the channel mismatch effect is shown.In experiment,the channel mismatch induced distortion in the sampling clock is measured via a frequency domain method and the spectral characteristics under different channel mismatch parameters are studied.Combining theoretical analysis and experimental measurement,the amplitude and time delay of each channel in the sampling clock are calibrated and the channel mismatch compensation is performed based on hardware adjustment.Eventually,the channel mismatch effect is suppressed and the quality of photonic sampling clock is effectively improved.Third,a high-speed PADC system based on TWI scheme is implemented based on the sampling clock generation.This study is conducted on the performance evaluation and channel mismatch compensation method.Theoretically,based on the established theoretical model,the performance evaluation of the PADC system and simulation of the channel mismatch effect are further derived.In experiment,the channel mismatch effect is measured via the digitized data according to the analog input with different frequencies.Under the theoretical guidance,a channel mismatch compensation method combining hardware adjustment and frequency domain algorithm is proposed and effectively eliminates the channel mismatch distortions in the digitized data.According to the evaluation of the experimental results,it can be found that the performance of the PADC has reached its theoretical limitation after channel mismatch compensation.In addition,the PADC system is also demonstrated with the reception and processing of wideband analog input signal,the channel mismatch compensation and performance evaluation method are also effectively extended to suit this case.Fourth,the pulse shape effect of the photonic sampling clock on the channel-interleaved PADC system is studied.The theoretical model is used to analyze the effect of pulse shape induced channel mismatchand its effect on the frequency response of the PADC system.In experiment,two PADC schemes with different pulse shape mismatch conditions are tested.According to the analysis of both two schemes and the comparison between them,the PADC scheme using photonic switch based demultiplexing avoids the pulse shape mismatch effect in the TWI based scheme,which ensures the feasibility of the channel mismatch compensation method and achieves a flat frequency response.Fifth,the time jitter limitation in the channel-interleaved PADC system is analyzed as well as the link noise.Theoretically,with the modeling of electro-optical sampling,photodetection and electronic digitization,it can be found that different numbers of demultiplexed channels and photodetection bandwidth would accumulate different time jitter in the digitized data.In experiment,the sampling clock jitter is suppressed by microwave photonic phase-locked loops.According to the measurement of electronic aperture jitter under different photoelectric conversion bandwidths,the bandwidth at half the single-channel sampling rate achieves the optimal time jitter,which also provides a convincing evidence for the breakthrough of “electronic bottleneck” in the PADC system.Sixth,based on the fundamental theory and key techonologies,a prototype of the PADC system is designed and implemented.Through an indepth cooperation within our research group,the architecture of the prototype is developed and its technical implementation scheme is carried out.The selection of system components is determined according to the application requirements and the prototype is packaged into modules according to implemented functions.When the prototype is completed,the digitzed data is calibrated by the channel mismatch compensation algorithm to guarantee that the performance reaches its expectation.