Design And Implementation Of High-Speed And High-Resolution Analog-to-Digital Converter

Along with the software radio technology, wireless communication, CMOS technology and development of SoC, speed and accuracy requirements for analog-to-digital conversion continue to increase, and the overall system accuracy is determined by the ADC. Pipelined ADC has a high conversion accuracy, and the characteristics of high-speed conversion, making itself suitable for high-speed and high-resolution applications. The research of pipelined ADC has become an important research direction in mixed-signal integrated circuits. High speed and high resolution analog-to-digital converter in the international community has a lot of commercial chips, while this type of chip is the product of domestic embargo. So that it is necessary to study in the field of high-speed high-resolution analog-digital conversion, and explore its design implementation.This work analyzes the main circuit blocks of the pipelined ADC, including the main sample and hold circuit, pipeline conversion level circuit, voltage reference circuit, clock circuit, and digital calibration circuit. A 14-bit 100MSPS pipelined ADC prototype circuit is designed in TSMC 0.18μm mixed-signal process. In this work, the design of the ADC prototype circuit has the following characteristics:considering the sampling switch on-resistance and nonlinear, CMOS switches, bootstrap switches are utilized; considering the high precision and high speed requirements of the analog-digital conversion, gain-boosting operational amplifiers are designed to improve the performance; considering the capacitor mismatch error, digital calibration algorithm is implemented. With advantage of high flexibility, and complex functions, digital calibration can effectively suppress or correct the non-ideal characteristics.The pipelined ADC prototype chip in this work includes capacitor-flip sample-and-hold circuit, pipeline stages, voltage reference circuit, and digital calibration circuit. After digital calibration, the ADC can reach an more than 70 dB SNR and an over 90 dB SFDR in system simulations; under 0.1% capacitor mismatch conditions, the digital calibration circuit can improve the SFDR more than 20 dB.