A 9-Channel 8-bit 1GS/S Time-Interleaved Analog-to-Digital Convertor For The Application Of DISK Driving System

The Analog-to-Digital Convertor, as a bridge linking the real analog world to the digital world, is a very important block in information transmission system. With the rapid development of Very Large Scale Integration and EDA tools, more flexible and reliable Digital Signal Processing technology has been the main orientation of design. Therefore, more attention has been paid to the design of ADC which is equipped with better performance of speed, resolution and power consumption. Time-Interleaved (TI) structure has been more and more popular for the application of high-speed sampling pattern. This paper proposes a solution for a 9-channel 8-bit 1 GS/s TI SAR ADC which is applied to the reading and riting system in DISK Driving.Firstly, some typical architectures of ADC are reviewed and the advantages and disadvantages of them are given. Then the TI ADC with different error mismatches effect is introduced. Later, three kinds of background calibration techniques are adopted to compensate offset, gain, and timing mismatches among different channels. The calibration techniques for offset, gain and timing skew mismatch are based on statistical expectation, on statistical variance technique and on average zero-crossing technique, respectively. Simulated in 9-channel 8-bit 1GS/s TI SAR ADC system, after calibration, the SFDR of the system is above 63dB, the offset mismatch is less than 0.1 LSB, the gain mismatch is less than 0.23%, and the timing skew is less than 3ps.SAR ADC, which is best suited to medium speed, medium resolution, and low power applications, is adopted in single channel. In DAC block, the value of capacitor unit is calculated manually and the linearity deterioration caused by capacitor mismatch and parasitic capacitors is deduced in detail. The offset of comparator introduced by mismatch is discussed. The crucial signal path is isolated as well as the system symmetry is optimized in layout. The rising and falling time of the SAR Logic block is designed carefully and the variable-delay clock buffer is optimized to the feasible place.This chip is implemented in SMIC 0.13um 1P8M COMS technology, and the area is 9.32mm2. The result of pre-simulation shows that, for the single channel SAR ADC, the ENOB is 7.95-bit, SFDR is 68.8dB, and FOM reaches 0.2pJ/conv.-step; for the TI ADC, after calibration, the ENOB is 7.67-bit, and SFDR is 61.4dB. The result of post simulation shows that, for the single channel, the ENOB is 7.3-bit, the maximum sampling speed is 100MS/s, and SFDR is 51.6dB.