Research And Design On High Speed High Resolution Pipelined SAR Analog-to-Digital Converter

High speed and high resolution analog-to-digital converters (ADCs) have a wide range of applications in the field of wireless communication. US control the export of high speed and high resolution ADCs. Therefore, the research of high speed and high resolution ADC is of great significance to the development of our country’s national defense industry and information industry. High speed and high resolution ADC used in the field of wireless communication utilized pipelined ADC in the past. However, with the progress of technology, the advantages of the pipelined successive approximation register (SAR) ADC in the high speed and high resolution field have been highlighted.This design adopts the pipelined SAR ADC structure, which has the following advantages. The traditional full parallel architecture is replaced by the successive approximation structure, which is used as a sub-ADC in this design. SAR ADC and the multiplying digital-to-analog converter (MDAC) share a sampling path, eliminating the problem that the sampling path does not match. Therefore, this design can eliminate the use of the front-end sample and hold circuit, saving the area and power consumption. Improved timing of this design increases the time of establishing for the operational amplifier, reducing the difficulty of the design of operational amplifier. In the first stage, the lower resolution is used to reduce the design difficulty of successive approximation analog to digital converter in the first stage. SAR ADC adopts tri-level charge redistribution technology, so that the number of units of capacitance decreased by 50%. Translation of transfer function increases the error correction capability of the ADC and reduces the complexity of encoding circuit.This thesis analyzes the selection of number of bits in per stage and sample and hold circuit structure, design method of high speed successive approximation analog to digital converter, structure selection and circuit design of operational amplifier. A11-bit 100MS/s pipelined SAR ADC is designed using the 65nm complementary metal oxide semiconductor (CMOS) technology. Simulation results show that it accomplishes 77.44-dB SFDR,65.95-dB SNDR and 10.66-ENOB for a 9.3-MHz 1-Vpp sinusoidal input signal at 100-MS/s sampling rate. With a 46.58-MHz input frequency, the 74.96-dB SFDR,65.93-dB SNDR and 10.66-ENOB are achieved.