Design Of 2.5 GSps 8 Bit Folding And Interpolating ADC

Since the 20th century,the application of digital technology in military affairs,aerospace and medical treatment has developed rapidly,with the development of digital information society,electronic products put forward more strict requirements for interface circuits that analog to digital(analog-to-digital converter).Folding and interpolating architecture is widely used in ADC with medium or high sampling rate(above GHz)and quantization accuracy(8bit-12bit).By the preconditioning input signal,there is not feedback loop in the whole architecture,Rough and fine quantization can operate in parallel,this architecture effectively reduce the number of circuit devices,the power dissipation and complexity of design.Based on 0.18μm SiGe process,the key circuit of a 2.5GSps 8bit ADC is designed with folding and interpolating architecture.The main modules of the circuit are:sampling and holding circuit,reference resistor network,folding circuit,interpolating network,digital coding circuit and so on.a topology with folding factor of 4 is proposed for the first stage folding circuit,and the coarse quantization circuit is removed by processing the middle signal.The layout of ADC is completed in this paper,The simulation with cadence shows that,power dissipation is 1.8W,SFDR is 53.86dB,SNDR is 45.21dB,ENOB is 7.058,INL is ±0.6LSB,DNL is ±0.18LSB with 3.3 V of supply voltage,58.6MHz of input frequency,2.5GSps of sampling rate。...