Research On The Error Sources And Calibration Technique Of SHA-less Pipelined ADC

As an interface between analog signal and digital signal processing(DSP) system, analog-to-digital converter(ADC) encounter more stringent requirements. To acquire higher speed and resolution, but consume less power at the same time. Benefit from the pipeline working and built-in redundancy, pipelined ADCs are widely used in wireless conmmunication and digital consumer products. Unfortunately a conventionally implemented pipelined ADC often consume significant power. The power dissipation can be reduced by eliminating the input sample-and-hold amplifier(SHA), while this introduce a serious drawback. The switched-capacitor of the MDAC and the sub-ADC in the first stage need to sample the dynamic input simultaneously. However, this synchronization is difficult to achieve in practice due to the edge misalignment in clock distribution and the inevitable mismatch among the two sampling channel, which lead to a sampling mismatch error. Thus, SHA-less pipelined ADC generally performs poorly at high input frequencies. Solving this problem is vital for a SHA-less pipelined ADC for IF sampling application. This is exactly what this thesis focused on.A brief analysis of all kinds of error sources was given primarily in this work., including noise, the S/H relevant error, the OTA error, the error introduced by the sub-ADC, the capacitor matching error, and particularly, the sampling mismatch error in the SHA-less ADC. A 12-bit 250MS/s SHA-less pipelined ADC, implemented in tsmc 65 nm CMOS process, was designed to assist the analysis. Based on a detailed analysis of the offset of the comparators, the architecture of three-stage pre-amp followed by a latch was established, employing the offset storage and cancellation techniques. The capacitor sizes are determined by capacitor matching and noise, which can be estimated by the constraint of linearity and quantization noise. The sampling mismatch between the MDAC and sub-ADC path was mainly discussed. As the causes of sampling mismatch, sampling clock skew and input bandwidths mismatch are quantitative analyzed, drawing a conclusion that the input bandwidths mismatch can be equivalent to a certain clock skew, and that the skew error increase as a function of the input frequency. The dynamic performance of the proposed ADC without calibration was tested. The SNDR fall to 56.3dB from 73.6dB with a sine-wave input increase from 11 MHz to 261 MHz,and the SFDR fall to 56.5dB from 88.7dB, seeing that the ADC suffered a terrible performance at high input frequencies, which agree with the analysis result.In this work, a mostly digital calibration technique was developed to treat the problem, which consists of three parts, the overflow detection unit, the digital control unit, the variable delay line. The overflow detection unit detect the output of the first stage and provide the digital control unit compared output, then control the variable delay line adjust the sub-ADC timing gradually achieve good alignment with the MDAC clock. Simulation result shows that the proposed calibration technique effectively restrain the odd harmonics at high input frequencies. When 261 MHz sine-wave input added, the SNDR increase to 68.7dB and the SFDR raise to 77 dB. A greater than 60 dB SNDR and 74 dB SFDR was still measured in the 4th Nyquist band. After calibration was employed, the SHA-less pipelined ADC achieved good IF sampling performance. The calibration circuits consume 3.1mW with a 2.5V analog supply and a 1.2V digital supply. The calibration technique implemented in this work has a maximum calibration range of 250 ps, which is completely enough for high speed pipelined ADC.