The Design And Realization Of Clock And Data Recovery Of Burst Mode

Fiber-optic access market is heating up,to light a next generation of access technology opportunities brought about by the rapid development.Passive optical network(PON) provides a low cast access technology for fiber to the home.PON works to solve the pivot of high-speed backbone network and local area network,or "last mile" problem.With the development of technology,costs continued to decline, PON has been widely used all over the world.Next-generation PON transmits at the rate of 10Gbit/s,and the large-scale deployment of 10G PON network is too costly.The rate of 1.25Gbit/s is hard to satisfy the Internet services which are more and more plentiful,so there is a need to select a middle rate of the transition as a next-generation PON technology.This paper analyzes the development of clock and data recovery,and designs a scheme of clock and data recovery at burst mode.This scheme needs to obtain the phase of the data,then adjust the local clock to the best sample point.It just only needs a few preamble bits to complicate the function of clock and data recovery.At the second part of paper,design a CDR thought oversampling.1.This paper discusses the circuit which suit for clock and data recovery at burst mode.This circuit includes a edge detector to extract the phase of high speed data, and trigger control circuit adjust the output of Voltage Controlled Oscillator dynamically.The output is located at the best sampling point.Analyzes the principle and performance.2.Using Pspice to verify the design,and modify the important parameters by the unit simulation.Using Simulink/Pspice to simulate the system.The simulation results show that the burst mode clock data recovery circuit based on phase alignment can complete clock and data recovery function.3.There are much difficult to achieve GHZ using discrete devices.Base on the features of the data structure and transmission of burst mode,this paper designs the other burst mode clock data recovery circuit based on oversampling what can custom build on FPGA.This design uses a new algorithm to choose the best sample point,reducing the complexity.And build a data transmission and receive system to verify the design.The result shows that the system can extract the data exactly,and complete the function of clock and data recovery.Furthermore,the system and the module of CDR can be synthesized,they can be built on FPGA, and reference to play the role of data processing of burst mode.