Clock multiplier unit and clock data recovery circuit for 10Gb/s broadband communication in 0.18mum CMOS

The clock multiplier unit (CMU) and clock data recovery (CDR) circuits are among the most critical analog/mixed-signal building blocks for the transceivers used in broadband communication systems. To date, such circuits with clock speed 10GHz and above are dominated by very fast, expensive processes. This work reports the design of the first CMU and CDR circuit in 0.18μm CMOS, integrated in a chip set of transmitter and receiver, with performance compliant with the stringent jitter specifications of OC-192 synchronous optical network (SONET).; New architecture and circuit techniques have been studied to overcome the speed and noise limitations of the CMOS technology. An LC-VCO with on chip inductor is employed by both CMU and CDR. Inductively tuned buffers connected in tandem carry the 10GHz clock signal to the distributed loads. In the CMU, a fully differential phase locked loop (PLL) is designed, with its phase-frequency detector, g_m-cell and divider all built with differential current controlled-logic. The CDR has a dual-loop architecture and uses a novel linear full-rate phase detector in a fully differential loop to achieve high jitter tolerance. Shunt-peaking techniques are applied to the limiting amplifier to enhance the bandwidth. In addition, circuit non-idealities have been investigated in detail to reveal their impact on the transfer characteristics of the phase detector, especially its strobe point and linearity. The study gives guidance on the power-speed-area trade-off and mismatch reduction in the phase detector design. Compared with the conventional design, the architectural advantage of the new phase detector is also further demonstrated.; High integration level and low power consumption are achieved by using standard CMOS technology with performances exceeding SONET jitter specifications. The jitter generation of the transmitter 10.66GHz CMU clock is measured to be 0.065UI_pp (unit interval, peak-to-peak) over a 50kHz to 80MHz bandwidth. The receiver CDR jitter tolerance is measured to be more than 0.4UI _pp for jitter frequencies between 4MHz and 80MHz, exceeding the specification by more than 100%. The transmitter and receiver dissipate a total power of 1.32W at 1.8V, much lower than other technologies. The CMU and CDR have also been integrated with network processors, showing solid performances.