The Design Of2.4GHz Frequency Synthesizer In TSMC0.18um CMOS Technology

As the second largest network after the Internet, Wireless Sensor Networkis the frontier hot research field with intensive knowledge, and is concernedinternationally. With more and more wireless sensor network began to put intopractical application. The demand of wireless radio frequency transceiver chip withlow cost, low power consumption, and high performance has become more and moreurgent. The frequency synthesizer is the indispensable important modules of WSNRF transceiver chip circuits, and phase locked loop frequency synthesizer is the mostwidely used type of frequency synthesizer.With the application of WSN as an example, this paper introduces the systemlevel design method of PLL frequency synthesizer, complete the whole systemspecific circuit design, former simulation through theoretical analysis, calculationand ADS-PLL Design Guide software iterative optimization method based on TSMC0.18μm CMOS technology, and designs a complementary cross coupling of LCvoltage-controlled oscillator, a dynamic D flip-flop circuit structure of PFD, anoperational amplifier and self-biasing cascode current mirror and supply-independentreference current source used in the CP design to reduce the influence of non-idealfactors. In this paper the loop system order number and filter parameters and otherimportant parameters are determined through the system level simulation model.Simulation results showed that the reference spurs reduced to-60dBc and thePLL achieved a phase noise of-124.3dBc/Hz at1MHz offset from the centerfrequency of2.4GHz, and current mismatch of less than0.2%over the outputvoltage ranging from0.3to1.6V with1.8V supply. The area of Chip is675μm×750μm, test results show that: phase noise of frequency synthesizer is about110.7dBc/Hz@1MHz, with1.8V power supply, current consumption of core circuitis about13mA, of which the VCO core circuit consumption is about5mA, CP circuit is about3mA, frequency divider and PFD is about5mA. Test results verified thevalidity of the design in this paper.