The Research On Multi-mode Reconfigurable PLL For GOS/Compass/TD-LTE-A Applications

This thesis proposed a design of the multi-mode reconfigurable PLL which is suitable or GPS, Compass and TD-LTE-A application.The detailed analysis and research on the nulti-mode PLL from system design, optimization of the phase noise and circuit mplement are presented.First, the thesis described the work mechanism of PLL. Each module’s contribution o the output phase noise in the PLL is analyzed, and the ways to optimize the phase loise is also discussed. In the part of PLL loop parameters design, the detailed flow to iesign a4-order PLL system which has best phase margin is provided. A system model n matlab and the system simulation are completed.Then, according to the results of system design, the specific circuits design are implemented. In order to improve the performance of charge pump, a novel charge pump based on the rail to rail operational amplifier is proposed. The proposed charge pump has perfect current matching characteristic and wide output range. A VCO with a tuning range of2.4GHz to3.2GHz is designed to meet the requirements of multi-mode applications. The VCO has a constant gain and the noise filtering technology is employed to optimize the phase noise. A MASH1-1-1sigma delta modulator is implemented to realize fractional-N frequency synthesizer. In order to reduce power consumption, the prescaler and multi-modulus divider is designed based on TSPC structure.Finally, a fully integrated fraction-N multi-mode PLL is design in SMIC180nm Mixed-Signal1P6M CMOS technology. The simulation and layout design are also completed. The area of the layout is about1.5mm*1.0mm. The maximum power consumption is11.51mW in each frequency band, the output phase noise is less than-117.4dBc/Hz@1MHz, and the lock time of the PLL is less than15us. The PLL meet the design specifications.