Research And Implementation Of Multi-stage Useful Clock Skew Technology

With the development of integrated circuits turning into nanometer process, timing closureis becoming more and more difficult. It has been proved by practice that useful clock skewtechnology(UCST) is a very effient way in optimizing timing, which can redistribute the slackbetween different timing paths by adjusting clock latency and then lend timing margin to criticalpath. UCST has been integrated into mainstream EDA(Electronic Design Automation) tools andshown obvious performance improvement, however, its application in EDA tools still has defect.The defect is that there are still many critical paths whose previous and next one or more stagesof timing paths have much timing margin which is not borrowed.According to the defect of EDA tools, Multi-Stage UCST is promoted and used toengineering practice. The technology has achieved further performance improvement after EDAtools’ optimization, reaching the excepted target. The main work of this paper is:1. Based on the basic principle of useful clock skew and EDA tools’ defect, this paper hasgiven a research on One-Stage UCST which can find the timing margin of previous and next onestage of critical path and lend it to critical path by adjusting the beginpoint and endpointregisters’ clock latency.2. Extended from One-Stage UCST, Multi-Stage UCST is promoted which will deeplysearch timing margin from previous and next multi-stage paths and borrow it by adjusting clocklatency for many groups of registers.3. The algorithm implementation flows are edited for One-Stage and Multi-Stage UCST.The special timing paths are identified and handled in the algorithm, such as feedback path, falsepath, path including asynchronous memory and so on, in order to ensure the completeness of thealgorithm. The two technologies are both implemented by tcl scripts, which are combined withEDA tool to realize automatic optimization and using simplicity.Testing with many modules which are deeply optimized through One-stage and Multi-stageUCST after EDA tool’s useful skew optimization, it is shown that the average performanceimprovements are4.36%and6.27%for each.