Rapid Design And Optimization Of Non-uniform Clock Mesh

Nowdays, the design of clock network is one of the most important andchallenging tasks in the design of modern high-performance microprocessors. Clockmesh structure, because of its features with small skew, small on-chip variation andstrong driving ability, is used for clock network in the design of high performancemicroprocessor. However, due to the special characteristics of the clock mesh structure,there are new design problems, on the one hand, the support of existing EDA tools isnot perfect, on the other hand the clock mesh with redundant features will produce a lotof power, all of these will limit the widespread use of clock mesh structure.From the perspectives of improving chip performance and reducing powerconsumption, this paper studies in depth the optimization techniques for the power andclock skew. We proposes a power optimization strategy with the goal of optimizing thewire length of clock mesh and drive buffer, and a clock skew optimization strategybased on partition of load boundary, while avoiding the disadvantages of existing EDAtools.The main work and achievements of this paper are as follows:First, this paper formulates the optimization strategies for the purpose of reducingthe power consumption of clock mesh and develops one algorithm for quickly planningthe global mesh based on the minimum of clock mesh wire length, which is also knownas the BDA. After BDA algorithm model updating, the power dissipation problemcaused by the line capacitance can be reduced by the maximum degree, and theneffectively reduce the power consumption of clock mesh.Second, this paper develops one adaptive drive buffer design method by taking theload boundary as the total predictive load of current drive buffer, and effectively solvesthe power consumption problems of traditional drive buffer design approach.Third, Aiming at the problem of larger clock skew of initial clock mesh, after theclear specific reasons, this paper proposes one optimization strategy based on thesecondary partition load boundary. The experiment results show that the method inexchange for increasing the smaller power consumption, and effectively solves theproblem of larger clock skew.Finally, take specific modules from engineering project to verify the effectivenessof the method presented in this paper, the validation results show that the method ofrapid design of non-uniform clock mesh compares with the traditional method ofuniform and non-uniform clock mesh design, the clock skew increases respectively by16.5%and6.015%, while the power consumption reduces respectively by20.2%and17.35%. Thus, in the case to ensure that the clock skew is not serious violation, it ispossible to effectively reduce the power consumption of the clock mesh structure. In this paper, our works is implemented in available software tools and engineeringscript, it has certain engineering value and reference significance of the widespread useand further study of the clock mesh structure in the design of high performancemicroprocessors.