Analysis And Optimization Of Consistency About Clock Skew Of Multi-corner

With the scaling of CMOS technology, associated with the complicating of applied environment and working condition of chips, global variations and local variations has became a paramount concern, which imparts a significantly adverse influence on performance of devices and interconnects. As a result, it has became increasingly challenging to design a clock tree with a high circuit performance while at the same time keeping an adequate stability in physical design. The synthesis and optimization of clock tree can be performed at only one corner with EDA tools based on multi- corner physical design, ignoring the clock deviation across diverse of corners. In this paper, the analysis and optimization of VMAC block is described based on YHFT-DX chips here. The mainly researching works of the paper are as follows.(1) We use VMAC module to illustrate the reason that affect the consistency of clock skew in multi-corner. By analyzing many results, we find that affect the consistency in clock skew in multi-corner main caused by the change of the delays in clock buffer units and the relatively large proportion of non-public clock path.(2) Based on 40 nm technology library, we analyze the clock buffer unit delay consistency in different temperature and voltage by simulating HSPICE, finding that the voltage is the main reason that affect of clock buffer unit delay consistency. In different voltage, the smaller times(from D0 to D6) in clock buffer unit, the worse the delay consistency, while the larger times(from D8 to D32), the better the clock buffer unit delay consistency. Experimental results show that use D8-D32 times to clock tree synthesis can get the best consistency of clock skew, Compared with the group of D0-D32 times, the consistency of clock skew increased by 6.8%, while compared with the group of the D0-D6 times, the consistency of clock skew increased by 10.8%.(3) By analyzing the topology structure and the characteristics of various clock networks, we find that the clock network grid type structure has a long public path as well as strong sensitivity in anti-technology. The level of support for the grid type clock network structure of EDI tools is not enough currently, while it needs a lot of human intervention. At the same time, we achieve a clock network In the VMAC module, based on semi-automatic clock mesh synthesis and manual tuning method. The EDI tool is based on the analysis model of voltage source for timing analysis of the design, while it cannot finish analyzing the timing of grid of clock with parallel driving structure. In this paper, we use the back annotation timing analyze method, which back annotation HSPICE simulation results to EDI tools. We analyzed the clock skew in VMAC module at different corner. By comparing, we find that the clock skew consistency using D8-D32 times for clock buffer unit to construct clock network is improved by 26.8% than using the structure of clock tree, while improved by 31.8% than using D0-D32 times for clock buffer unit to construct clock tree.Above all, the problem of clock skew consistency in multi-corner can be commendably optimized by using preferable delay consistent clock buffer unit and clock network structure, which could get a nice result in practical work.