Design Of A TDC Based On The Delay Locked Loop

Recently with the development of process technology, the line-width ofintegrated circuits decreases continually, analog integrated circuits often can’t meetthe required SNR(signal noise ratio) and output range in the technology scale lessthan100nm. However digital integrated circuits can be obviously improved eitherin switching speed or in chip area due to technology scaling. Digital integratedcircuits are good at processing time signal which is expressed as time-to-digitalconverter. Hence, some analog integrated circuits are realized by TDC in ultra deepsub-micron process. In addition, TDC also plays an important role in high-energyphysics and atom field to finish high precision measurement. So the research onTDC is meaningful both for IC design and high precision measurement.Recently some foreign researchers have finished the TDC design based onboth FPGA with few hundreds ps’s resolution and full-custom MOS delay lineswith few ps’s resolution, however the TDC design in China which is almostfulfilled by FPGA is far behind that abroad, so further research on TDC should bemade.A synchronized hierarchical TDC which is based on a delay locked loop isdesigned with full-custom MOS delay lines in0.35μm mix-signal CMOS process.This article introduces the basic performance figures and architectures of TDCs atfirst, then discusses the DLL design. A DLL with a novel phase frequency detectoris adopted to resolve the problem encountered in traditional DLL and its inputfrequency can range from45MHz to125MHz. The phase offset of the DLL are1ps、2ps、4ps in tt、ss、ff process corners, which is less than the resolution ofthe TDC. Finally the designed DLL is applied to the TDC. The TDC includes thefollowing three quantization levels: the carry look-ahead adder based counter、theDLL based Fine-TDC and the Dual-DLL controlled Vernier-TDC. With a100MHzclock, every module of the TDC is designed and the simulation results of eachmodule and the whole TDC are done by Spectre. At last, the TDC’s transmissioncurve is achieved, the valid resolution of the TDC is about9.7ps.The designed TDC has advantages of less area、lower power consumption andfast conversion speed without extra calibration.