Design Of A Delay Locked Loop Circuit Applied To The TDC

With digital signal processing and conversion speed between analog and digital signals becoming faster and faster, as an integral part of integrated circuits and electronic products terminal, the excellent design of clock circuits is increasingly critical. The requirements of clock are particularly stringent especially for measurement and conversion circuits, such as TDC and ADC. And clock quality is related to all aspects:accuracy and conversion efficiency and so on. Changes of process, temperature and other conditions have a great influence on the clock frequency for voltage-controlled oscillators. Because of their unique advantages, phase-locked loop or delay locked loop has more extensive application in the clock fields.In this thesis, considering the requirements of high quality clock to realize the time digital conversion function for TDC, proposed a new DLL system architecture on the basis of extensive research. Wide dynamic range, low static phase error and low jitter are the focus of DLL in this thesis. Taken certain measures in various aspects of system architecture, module circuits and layout drawing, to ensure the performance of DLL. In system architecture, dual delay lines and anti-false locked control circuit are used to extend DLL lockable frequency range. In the charge pump(CP), idle current diversion, wide swing cascode structure, the same type of switch, switch branches away from the output and other measures is used to achieve a better match between the charge and discharge currents, and inhibit charge-sharing and other non-ideal effects. Thus it can reduce the static phase error and and the clock jitter of the output after DLL locked. Buffer circuit of the phase detector is used to match the delay information, and reduce the CP output current error. In layout design, good layout planning, matching design of transmission path, isolation design of mixed and sensitive circuits, shielding design of high-frequency signal lines are adopted to reduce the parasitic interference and crosstalk between modules.Based on TSMC 0.35μm CMOS process, the DLL is simulated and layout-drawn by spectre and virtuso of Cadence, and verified of MPW tapeout in this thesis. The simulation results of clock range, static phase error and clock jitter can all meet the application requirements of TDC. The test results show that, in different SO signal, DLL can respectively lock in 40MHz-80MHz and 105MHz-190MHz; in different state, static phase error is 178ps@125MHz, at different frequency, the error is less than 5%; compared with the input clock source, a rough estimated of DLL jitter:pk-pk jitter is up to about 40ps, RMS jitter is up to about 6.7ps. The DLL has the locked function and certain performance. However, the lock frequency range becomes narrow, and the static phase error and jitter performance have some gaps compared to simulation results, which is related to DLL design flaws, test conditions, test methods and so on.