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Research And Realization Of FPGA Switch Parameter Test Method

Posted on:2015-03-16Degree:MasterType:Thesis
Country:ChinaCandidate:Q ShaoFull Text:PDF
GTID:2208330464963412Subject:Microelectronics and Solid State Electronics
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With the rapid development of Field Programmable Gate Arrays in recent years, today FPGA chip’s integration has reached ten million. Modern FPGA chip is directing to higher density and higher capacity and its complexity is gradually increased. How to test FPGA chips quickly and efficiently becomes the hot topics in academia and industry in recent years. The research and test of switch parameters, which indicate the FPGA performance, occupies a large proportion of FPGA testing. Now the method of measuring this time interval is using Time-to-Digital Converter in FPGA testing area. The circuit structure gradually developed and has become a dedicated circuit structure of the industry. Here come two problems during practical testing:the low resolution and the reducing accuracy according to the change of temperature. The switch parameters test method in this paper is to solve the problems above.A single tapped-delay-line TDC with digital DLL based on FPGA is presented in this paper. It solves the problem of low resolution of TDC which is using FPGA configuration circuit and the accuracy of TDC reducing with variation of temperature. Tapped-delay line TDC is selected. The dedicated fast carry line in FPGA is chosen. The resolution can achieve 167ps in the temperature of 25 ℃ based on a process of 0.18μm FPGA. Thanks to the feedback of digital DLL, the delay line can adjust its delay according to the variation of temperature. And we can get each delay cell’s delay so that this circuit is able to test the switch parameters with the variation of temperature. Compared to a TDC implemented on an Anti-fuse FPGA, the resolution of this circuit improves 16.8%,16.5%,16.7% in the temperature of 0℃,25℃,50℃ respectively. The variations of resolutions are almost the same based on the same variation of temperature. The coding line of TDC in Anti-fuse FPGA requires many redesigns however the TDC in this paper adjusts its delay line by DLL feedback which may reduce the cost and time in the process of design and develop greatly.
Keywords/Search Tags:Field Programmable Gate Array, Time-to-Digital Convertor, tapped-delay-line, digital delay locked loop
PDF Full Text Request
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