Improved For The Fpga Digital Phase Locked Loop Circuit Design,

This paper designs an on-chip DLLs using digital architecture which modified analog modules as VCOs,LPFs which traditional DLLs used, into digital realization,thus prevent flaws as lack of stable model, sensitive to noise,difficult to re-use.This design also ameliate the flaws of area consuming and disability to large range of frequencies which traditional digital open-loop and lock-loop DLLs possessed.This design allows for synchronization of external and internal clocks in FPGAs.This design applying SMIC 0.18μm process,this delay can operate under frequency ranges from 10MHz～250MHz.DLL's locking time is within 150 clock cycles(15μs(10MHz)～0.6μs(250MHz)).The locking process is one-shot,and does not need constantly re-synchronization.This design is in-sensitive to noise,and only consume far less silicon area and resources than other approaches.In addition to providing zero delay with respect to a user source clock,the DLL can provide three phase-shifted version of the source clock.The DLL could provide duty cycle correction on all output clocks such that clock outputs have a 50%duty cycle.The DLL can also divide the user source clock by up to 32.The values allowed for this property areBesides this design can also realize programming phase shifting, providing 0°90°,180°,270°4 types of phase shifting output;duty cycle adjustment,providing 50%duty cycle output;and plus frequency synthesis,providing frequency doubling and frequency de-multiplication ranging from 1.5 to 32.