Research On Key Technology Of 2Gbps Clock Data Recovery Circuit

As the frequency of the interface increases,the problems of parallel transmission technology used in practical applications have become increasingly prominent.In order to overcome the limitations of the traditional parallel transmission technology,engineers have developed a high-speed serial transmission technology based on differential signal transmission and it gradually becomes the mainstream of communication.The clock data recovery circuit(CDR)is the core module for high-speed serial transmission technology,so it is very important to study low-noise,low-power CDR circuit and its key technology.This thesis briefly introduces the basic concepts of high-speed I/O transmission system.Several basic structures of CDR circuits are described.The loop characteristics and noise characteristics of the PLL are analyzed to optimum the performance of the system phase noise.The advantages and disadvantages analysis between LC voltage-controlled oscillator and ring voltage-controlled oscillation is performed to determine the more suitable oscillation scheme.The frequency-locked loop and phase-locked loop of the CDR circuit are studied.Based on the above theoretical analysis,the structure of semi-digital dual-loop circuit are used here to design a 2Gbps clock data recovery circuit in the SMIC 0.18?m CMOS standard process.In order to solve the problem of bandwidth contradiction of CDR circuit based on the traditional PLL structure,we adopt relatively independent frequency-locked loop and phase-locked loop.In the phase-locked loop,a half-rate Alexander phase detector is used to reduce the reference frequency to one-half of the operating rate,which greatly reduces the design difficulty of the ring VCO.Phase control and regulation are implemented with digital circuits to reduce the impact of process changes on the system and make the design easy to adjust and transplant.Based on the simulation and optimum of the frequency discriminator circuit,the charge pump circuit,the second-order passive low-pass filter circuit,the ring voltage-controlled oscillator circuit,the divider circuit,the buffer circuit,the phase interpolation circuit,the phase selection circuit,the clock shaping circuit and other functional modules of the CDR circuit,the simulation of the overall system is obtained.The simulation results show that the frequency tuning range of the ring VCO is about 0.65GHz~1.3GHz,the gain is2.42GHz/V,the phase noise is-98.93d Bc/Hz(@1MHz)at 1GHz frequency,the output frequency range of the CPPLL is 0.75GHz~1.25GHz,the center frequency is 1GHz,the power consumption is 7.57mW(@1GHz),the jitter of the quadrature clock recovered by the clock data recovery circuit is about 24 ps and the power consumption is only 35.8mW when the system receives 2~7-1 pseudo-random NRZ code.