2.5 Gbps Clock Data Recovery Circuit Design

The dramatic increasing in processing power has rapidly scaled on-chip aggregatebandwidths. As data rates enter the multi-Gbps range, the high speed serial datacommunication architectures becomes attractive as compared with traditional parallelarchitectures and gets a widespread application.In serial data communication systems, the CDR circuit is responsible for extractingand regenerating a reasonable clock signal, and recovering data from the incoming datastream. The recovered clock removes the jitter and distortion in the data by retiming andde-serializes data stream to parallel for further processing. It impacts the wholeperformance of serial link system.This dissertation describes a CDR circuit implementation based on the0.13μm1P8M CMOS process, which works at2.5Gbps data rate. With the merits of relativedependence between frequency-tracking loop and phase tracking loop, the semi-digitaldual-loop topology is used to resolve the loop bandwidth compromise problem ofconventional PLL-based CDR. We adopt the half-rate clock topology to reduce theworking frequency of ring VCO. A half-rate Alexander PD is adopted in phase-trackingloop, and the generated clock phase is controlled and adjusted by digital implementedcircuit, to reduce the sensitivity of process change. It makes this work can be easilytransplanted to multi-channel applications with a single frequency tracking loop toreduce the power consumption and layout size. The main topics of research are asfollows:(1) Based on the analysis of PLL theories and transfer functions, a low jitter PLL ofwhich the output frequency is1.25GHz, is designed, a self-biased topology is adoptedto achieve a good rejection to power supply noise.(2) The research of phase adjusting and phase interpolators. We analyze the phaseadjusting principles in phase-tracking loop, especially the elements which affect thelinearity of phase interpolator. The PI is implemented based on the analysis andcontrolled by digital circuit, so we can acquire a more accurate clock signal in phase.(3) The research of layout design of high-speed analog and mixed signal circuit. Several noticeable items are emphasized in the layout design, common problems andthe way to resolve them are enumerated also.The whole design occupies1.97mm~2, of which the CDR takes up0.46mm~2, and thesimulation results show that the jitter of the recovered clock is34.7ps, and the powerconsumption is53.6mW with the NRZ pattern of271.