Research On Ultra-low Power And High Reliability Nonvolatile Memory Cell Based On Standard CMOS Process

Muti-time Programmable(MTP)memories,which are based on standard CMOS process,can be widely used in SoC such as RFID tag chips,and becomes a research hotspot in recent years.The design of MTP memory cell should take into account the requirements of program/erase efficiency,power,area and reliability,et al.Therefore,the cell design is the key to the performance of MTP memories.The main research contents include the following aspects:1)Three MTP memory cell structures with different characteristics are proposed.First,a pseudo differential cell structure is presented,which can output differential currents,while the occupied area is equivalent to the single ended structure.Second,a new MTP cell based on improved n-well capacitor is proposed,through preventing from deep depletion state the cell achieves faster and more stable writing speed.Third,a method that can improve the cell's erase efficiency is proposed,the erase efficiency is greatly improved compared with the traditional MTP cells.2)A compact model for the MTP memory cells is proposed.Based on the charge balance equation,a method to accurately calculate the floating gate's potential is presented.The experimental results of the new model and the traditional model are compared,the differences between the two models are analyzed deeply,and the flow of transient simulation of the MTP memory cells is given.Finally,it is discussed how to optimize the MTP memory cells by using the proposed compact model.3)A endurance model is established for the MTP memory cells.First,a new electron trapping-detrapping(T-D)model is proposed,which is able to simulate the oxide bulk traps' occupation state and the electron detrapping effect.Then,the relationship between the generation of oxide traps and the stress and duration time is explored and modeled.Finally,the effects of the oxide traps on the device's tunneling current and threshold voltage are studied,and an endurance simulation procedure is presented for the MTP memory cells.4)A retention model is established for the MTP memory cells.First,the relationship between the recovery of oxide traps and the temperature and duration time is explored and modeled.Then,all the leakage paths faced by the floating gate of the MTP memory cell are studied and modeled.Finally,a retention simulation framework is proposed suitable for the MTP memory cells,which supports the Monte-Carlo analysis,and can be used to predict and optimize the statistical distribution of the MTP memory cells' data retention characteristics.