Design Of The Charge-Pump PLL Based On The 65nm Process

With the fast development of technology, 65 nm CMOS process technology has gradually become the mainstream in parallel with the frequency elevation. It requires high performance PLL(Phase-Locked LOOP) circuit to generate high-quality clock signal in 65 nm CMOS process technology. The PLL design will face greater challenges and difficulities in the more advanced technology. One of the main challenges is that the leakage current becomes significant. For the mixed-signal circuit, it severely degrades the performance and results in high standby power consumption .What's more, the supply and substrate noise result in high output signal jitter in PLLs. With the clock period decreases, the tolerance of clock jitter is confined to narrow limits.This paper proposed a CPPLL with consideration of the main design points of PLL and the characteristic of IC design with the 65 nm technology. The major contents and highlights of the research are as follows:1. The thesis advanced the speesd of charge and discharge by introducing many group of UP-DOWN transistors and charging them beforehand. Since each MOS transistor has different size, it can provide different current for charging and discharging, moreover, it reduce the locking time of CP. We improved the stability of CP and reduced the power by adding an operational amplifier circuit.2. Designed an oscillator which based on digital single-ended ring structure, whose main body merely consists of inverters and transfer-gates. The VCO can produce 8 clock signal which has same frequency and each adjacent phase difference isπ4 . As the Hspice simulation results show, the frequency of the clock signal well meets the requirements and it is quite reliable.3. The PLL can provide different frequency clock signal by programmable divider which extent the range of divide-factor.sssss4. In the layout design section, we study the characteristic of digital-analog layout design, finished the the layout design of PLL with reasonable placement and elaborate routing, then carried out DRC, ERC, LVS assessment building on this. The Hspice simulation at the circuit-level and layout-level were also satisfy requirements.