Design Of BiCMOS PLL For UHF Receiver

With the development of communication technology, the ASK (Amplitude Shift Key) receiver, which works at 290MHz~500MHz , is widely used in the field of domestic security, auto control and entrance guard systems. PLL (phase locked loop) as the core of the receiver has the great significance on it. The purpose of this thesis is to research the PLL frequency synthesizer suitable for ASK (Amplitude Shift Key) receiver. Based on the specification of synthesizers, the Simulink models are established to analyze the charge pump phase-locked loop (CPPLL) in this thesis. And the PFD (phase fequency detector), charge pump, VCO (voltage control oscillator) and divider modules are presented.Several characteristic works in this dissertation are summarized as follows:1) The phase frequency detector (PFD) and charge pump circuits are designed for no dead zone. And the power consumption is minimized by optimizing the traditional D flip-flop structure. The area is decreased by substituting active load for resistors.2) To improve the frequency and speed performance, the first divide-by-2 circuit is reformed. And the stacked-mode is adopted in the divide-by-4 circuit; through reusing the bias current, the power consumption of divider is reduced.3) In the design of voltage controlled oscillator (VCO), a varactor model is established in VerilogA language. The VCO circuit is successful simulated through Cadence Spectre with this model.4) The whole circuit is simulated through Cadence Spectre. According to the character of Mixed-Signal circuits, the layout is proposed. The whole chip is fabricated in AMS Mixed-Signal BiCMOS 2P2M 0.8-um technology.Finally, the result of chip test indicates that the total power consumption of PLL circuits is 2.3mA with 5V supply voltage. The phase noise at a 100kHz offset is -98dBc/Hz. The whole PLL circuits meet the specifications of ASK receiver.