An11-bit1MS/s SAR ADC With A Set-and-Down Switching Procedure

In the realm of modern signal transmission and processing, the power of digitalsignal processor (DSP) and central processing unit (CPU) on processing digital signalis growing, accelerating the penetration of digital signal processing technology to allcorners of our modern society.Analog-to-digital converter (ADC), which acts as thebridge connecting digital world and the analog world, has been widely used in radar,communications, monitoring, control systems, and other signal processing systems.The performance of higher level system is often decided by ADC.With the improvement of ultra-large-scale integrated circuit manufacturing, andthe popularity of computer-aided design technology in engineering, ADCimplementing with new ideas, new structure and new performance emerge to meet thedifferent requirements of control systems and signal processing. With the rapiddevelopment of computer, multimedia and internet technologies, the need ofhigh-performance ADC will drive designers and producers to design new structureand develop higher level manufacturing technology, respectively. With the big marketand good prospects of ADC, it’s very important to study analog-to-digital converter.This paper presents the design of an11-bit1-MS/s successive approximationregister (SAR) analog-to-digital convertor with a set-and-down switching procedureusing0.35μm CMOS process. The switching procedure of capacitor network isinvestigated. The result shows that average switching energy consumption is reducedby81.25%and that the number of unit capacitor is also reduced by50%, comparedwith conventional11-bit SAR ADC. Post simulation results also show that Signal toNoise and Distortion Ratio (SNDR) and Efficient Number of Bit (ENOB) reach66.6dB and10.7bit, respectively. With0.35μm2P3M CMOS process, the circuitlayout is realized. This SAR ADC layout occupies an area of705μm×412μm.