The Study Of Ultra-High Speed Sampling Based On Multi Channel TUADC

High speed sampling is widely used in radar echo detection, Particle physics experiment, pulsed laser ranging. Besides, high speed sampling is the core modular in advanced sampling devices such as ultra-high speed oscillator and logic analyzer. Amid the implementations in high speed sampling, Time Interleave ADC is one of the most important topics.To improve the accuracy of TIADC high speed sampling, and to facilitate the problem of channel extension, the following three parts of TIADC system is studied:1) The study of signal distribution and symmetry of power divider modular. The three sections of study include the single/differential conversion, the channel expansion of input signal, and the impedance matching of the system frontend. Simulation and experimental results showed that signal distribution in power divider has good inter-channel consistency and low loss.2) The study of stability and expansion of multi-phase clock. The three sections of study include the phase noise of sample clock generation, the implementation of channel expansion, and the optimization of the system workflow. Jitter in multi-phase clock distribution is below200fs, while preserving channel expandability. TIADC system achieved SNR of67dB at4GSPS.3) The study of ultra-high speed data caching. To achieve48Gbps ultra-high speed data caching, a deceleration based on FPGA PingPong mechanism is devised.12Gbps data caching was achieved in a single modular.Finally,4GSPS multi-channel sampling experimental result is given. The experimental result show that the expected system performance is met.