| High-Speed clock distribution is greatly challenged by the following critical problems, clock delay, clock skew, and power minimization. It further requires that these criteria be evaluated with real signal waveforms or circuit simulations, since simplified circuit models usually hardly provide accurate information on the circuit performance.; In this thesis, an automatic clock routing CAD tool for high-speed VLSI designs is proposed. Algorithms for unifying the techniques of planar clock routing, tapping point adjustment, and bottom-up buffer insertion are presented. Furthermore, the CAD tool integrates the individual tasks in an efficient and effective way such that high speed clock distribution design with minimal delay, Skew and power can be achieved in a reasonable design time.; First, a set of heuristic algorithms has been developed for the planar clock routing with treatment of obstacles. Second, tapping point adjustment technique is integrated to minimize the clock skew and delay of the unbalanced clock tree. Third, the CAD tool offers the problem analysis of computing the position and size of buffers given all design constraints, and includes a buffer insertion algorithm for optimizing high-speed clock tree. Finally, in order to evaluate the clock circuit performance at such a high frequency, the CAD tool uses a fast circuit simulator which is able to provide full waveform evaluation with an adequate speed. |
