Research On Low Cost Test Method For RTL Data Path Under Power Constraints

Large scale integrated circuit production needs test to ensure its yield, the test hasbecome an integral part of IC production. However, the transistor density ofintegrated circuits increase exponentially, led to increasingly high cost of testing, ICtesting as a result of current research challenges. Expensive testing costs and highpower consumption has become a bottleneck for developing VLSI test, in order toreduce test application time,high-level especially RTL design for test become aresearch focus of testing with low cost.First, for the register transfer level (RTL) data path, this thesis proposes linearshift controlled built-in self test method. The approach combines gate level scan testand BIST test, with low hardware overhead and short test application time. Controlledlinear shift is composed of linear shift register and controller, use register in RTL datapath as shift register, by import single bit to highest bit of shift register to product testvector.Second, this thesis presents a new test generation method to study and use thestructural features of functional modules in the RTL data path, combined with sideshift-while-scan test methods, to test the modules to reduce test application time andhardware overhead. the general structure of the adder, subtracter and multiplier areformed by full adders and half adders, the test gerneration can be composed of a fulladder’s (or a half adder’s) test vectors.Third, for RTL data paths, this thesis presents a test synthesis and testscheduling.During Synthesis in the test, we propose a heuristic approach to assigneach test module for the response analyzer and linear shift register; in test scheduling,an improved algorithm proposed, using change of test resources in unequal length test,increasing the number of test set during a test session to reduce test application timeunder power constraints.Finally, for usual RTL data paths, the test vector can be generation by proposedmethod. Experiments show that: test application time reduced, up to13.2%.the thesisalso discuss different number of grouping for shift register impact on the testapplication time, results show that the test time decreases with the number increaseswith structure in a given case.