Research On Design For Testability Of ASIC And Embedded Memories

Since the evolution of integrated circuits has developed to the point where a large amount of transistors can be integrated on a single chip, the functions of ICs become more and more complex. In addition, because of the increasingly pressing demand coming from the market, the design periods are shortened, and the method of using standard pre-designed IP model to construct the chips become mainstreams, which cause to the increase of manufacture faults and at the same time the testing become more and more intractable. Then design of testability comes forth. At present, considering testing periods and full speed testing, the demand of testing can not be reached even though the traditional DFT such as scan chain is used. However, if the testing method based on built-in self-test is adopted, it will not only reduce the testing periods but also accomplish full speed testing.In this paper, the BIST method for ASIC which performs the 4096 points FFT is presented. In Chapter Two, the methods of DFT are introduced. Then a comparison is made according to their characters and the application scope of each method is determined. From that we get the whole scheme of DFT for FFT, which is using BIST in DFT of the multiplier and memories. Chapter Three presents the detailed introduction of the theory and circuit structure in each part of BIST. Chapter Four takes example for the high speed 16*16 fixed-point multiplier used in the circuit to introduce the design of functional circuits and the structure of BIST circuits. Since the circuits of FFT need a large number of memories to accomplish the acceptance of data and the storage of middle results, nevertheless it is difficult and slow to test SRAM exteriorly, in following Chapter Five we improve a test algorithm through the analysis of fault models and testing algorithms in embedded memories. At last, we use the technique of BIST in Design of testability of SRAM. In the summary of the whole paper, it also presents the detailed originality of the work. It is proved that the request of testing devices is reduced by using BIST. Moreover it can perform full speed testing. Consequently we can reduce the cost and abridge the testing steps and then obviously improve the testing efficiency.