| Present day microprocessors, such as Pentium-D and Core from Intel Corporation, are fabricated using the 65 nm technology. Around 300 million transistors can be packed into two square centimeters of chip area using this technology. Improvements in fabrication technology are enabling the semiconductor industry to keep up with Moore's law which states that the number of transistors on integrated circuits will double every 18 months. Increasing transistor density enables designers to offer customers more functionality per unit area. This indirectly also increases the chip complexity.; The present day fabrication technology is sensitive to a large number of process parameters such as temperature, pressure, dopant concentrations, etc. Small process variations can induce defects into manufactured chips. Such chips need to be tested to prevent defective parts from reaching the market. The defects can be detected by modeling them as faults in the circuit design, such as stuck-at faults, delay faults, etc. Tests for these faults are generated based on a given circuit description. Most of the existing automated test generation techniques use the gate-level description of a circuit. This coupled with the chip complexity make it very difficult to automatically generate tests for targeted faults. Most of the successful test generation approaches modify the design to reduce circuit complexity which in turn reduces test generation time. However, such approaches are not suitable for high-performance designs such as microprocessors.; Increasingly, there is a trend towards initiating circuit designs at higher levels of abstraction. Designing circuits at higher levels reduces the number and length of design iterations, time-to-market and costs associated with the design process of an integrated circuit. Also, the number of components required to describe a circuit at higher levels is lower compared to the corresponding gate-level description. This feature has been successfully exploited by performing test generation at the register-transfer level which in turn reduces the test generation time. However, such techniques are feasible only if certain restrictions are imposed on the circuit. Examples of such restrictions are separable controller and datapath, complete controllability of signals at the interface between controller and datapath, state table or state transition graph description of controllers, circuit description at a single level of design hierarchy and so on. A majority of these restrictions prevent these test generation techniques from being applicable to practical industrial designs.; In this thesis, we present a satisfiability based test generation technique that targets stuck-at faults in a design and exploits any high-level constructs in the circuit description for reducing test generation time. (Abstract shortened by UMI.)... |
