The Study On Built-in Self-test (BIST) For Integrated Circuits Based-on Multiple Scan Chains

As the integration density of the integrated circuits increase, more and more functionality can be packed into a chip, which is called sytem on chip (SoC). This requires a significant increase in test generation difficulty and results in large test data volumes. Application of these test data requires sophisticated, high speed automatic test equipment (ATE) and long test time. So test cost is very high, typically is order of several Dollars per minute. Besides, the number of pin counts grows at a slower pace than silicon density, limiting the increase in test application bandwidth and lengthening the test application time. Furthermore, the semiconductor technology of products under test is ahead of the technology of ATE. So it may not provide at-speed testing.Built-in Self-test (BIST) offers an attractive alternative to conventional external testing methods. By moving test generation, application and test response into the chip itself, BIST eliminates the need for expensive ATE, reduces the test cost and can provide at-speed testing. The thesis addresses several issues related to BIST for multiple scan chains.Initially, several basic concepts and methods about design for testability (DFT) and SoC test techniques are introduced.Secondly, logic BIST is extensively studied especially test pattern generation techniques. Exhaustive testing, pseudoexhaustive testing, pseudorandom testing, weighted testing and "store and generate" testing are described in detail.Thirdly, an improved design algorithm of phase shifter is proposed. Phase shifter can overcome the data dependency among scan chains during pseudorandom testing and plays an important role in the improvement of fault coverage for circuits under test (CUT). On the base of previous phase shifter algorithm, the proposed algorithm selects xor taps by the way of an added pseudorandom sequences generation function. The experiment results show that the proposed algorithm not only avoids previous phase shifter design algorithm disadvantage which results in too many fan-outs in LFSR, but also improves the fault coverage. The phase shifter designed by the proposed algorithm has some practical usefulness during pseudorandom test and mixed mode test.Finally, constraint input reduction, linear feedback shift register (LFSR) coding and folding counter are applied to compress and generate a deterministic test set. After constraint input reduction, not only the bits of each test pattern are reduced significantly, but also the care bits are reduced. So the bi-seed test method that combines LFSR coding and folding counter can be used furthermore to compress test sets. The highlights of the mew proposed technique are effectively combining previous several test methods and taking full advantage of the methods in test data compression. Compared to international similar approaches, the proposed technique needs less storage volume,can reduce testing time significantly,fully upgrade test performance,and is compatible with traditional scan-based design flow.