Research On Built-in Test Technology For Communication Equipment

Nowadays,information technology and semiconductor manufacturing process improve dramatically,resulting in great improvement of equipment performance while its complexity also increases.Aimming to ensure maintainability,reliability,availabitiy,logisticsand readiness capability and others,the fault diagnosis test has gone through the development stage from simple to advanced,from external to internal,and the designs for testability has also become the key to the early stage of equipment design.Based on the above background,this thesis researches and implements the BIT technology of a communication equipment,and designs a BIT hardware platform for fault diagnosis and testing of communication equipment.The main research contents are as follows:1.In terms of the GJB2547A-2012 requirements for BIT,as well as the analysis of each module circuit and function of communication equipment,the basic model of the BIT system of communication equipment is established.In view of the difference between the electrical characteristics of various modules and test signal,the test points inside system are selected as well as the corresponding test parameters and methods.2.Based on the module test and maintenance bus in IEEE 1149.5,the BIT test system architecture proposed can realize the broadcast communication between the main system and the hierarchical test system unit.3.Radio/Intermediate Frequency BIT circuits are designed in response to the test requirements of the passive test points obtained in the test model.Taking into account the constraints of BIT,Single-range and wide-band passive structure is given.4.To measure the active test points obtained in the test model,referring to the IEEE 1149.1 protocol standard,a digital BIT sub-system is designed to realize the boundary scan test function of the digital chip.At the end of the thesis,the standard signal source is used to simulate the signal at the test point in the communication equipment,and the test command is issued through the upper computer software to test and verify the performance index of the designed test platform.