A Study On A Test Method Of Internal Functional Modules Generating Test Vectors For RTL Data Path

Test is an indispensable procedure of integrated circuits production. With the development and advancement of new materials and manufacturing technology, the density of transistors in a chip increases exponentially, which makes integrated circuit testing more complicated and expensive. Therefore, the testing of integrated circuit becomes a challenge to our current research. IC test power consumption, test application time and hardware overhead during testing are the bottleneck, among which low-cost test, on the purpose of reducing test application time, is the key point.Among the register-transfer level(RTL) data path testing, non-scan BIST is an effective test scheme, which can achieve at-speed testing and the test application time is short. However, its hardware overhead, power consumption is too high.This thesis presents a new test method, where we studies how to use the internal function modules of RTL data path, such as adders, subtractors, multipliers as hardware to generate test vectors which can test the modules under test to reduce the test application time and hardware overhead. The principle of the adders and subtractors to generate test vectors is the same as that of accumulators. For a traditional multiplier can not produce all test vectors, we modify the structure of the multiplier, such that in test mode, the enhanced multiplier can generate all the test vectors that we need. In addition, for RTL data path, this thesis proposes a test synthesis and scheduling approach. In the test synthesis process, this thesis introduces a heuristic algorithm to assign test pattern generators and response analyzers to the modules under test. In the DFT process, this thesis describes a cost function to evaluate the test application time and hardware overhead. In the test scheduling process, this thesis employs incompatible graph and left edge algorithm to schedule the modules under test. The proposed test synthesis and test scheduling algorithm has good performance and practicality. The experimental results show that, under the given power constraint, for three data path Paulin, Tseng, LWF, the test application time can be reduced up to 22.4%. Furthermore, its hardware overhead can be cut by a large degree,73.4% to its utmost.