Research On Accumulator-Based Built-In Self-Test For DSP Data Path

With the rapid development of System-on-Chip technology, it brings challenges to the testing of all kinds of VLSI which include Digital Signal Processor (DSP). Built-in Self-Test (BIST) has become an important approach for testing VLSI that reduces test complexity and cost. Because reuses of some adders in VLSI as generators of test patterns (TP) and compactors of test responses result in reduction of additional hardware overhead for the VLSI test, accumulator-based BIST has good performance and has recently been highly recognized in VLSI test research field. This dissertation reports an investigation on accumulator-based BIST for DSP data path. Major works for this innovative research consist of five aspects as followings:1. In BIST environment, A scheme of Design-for-Testability for DSP data path is proposed and investigated based on scan path method. For the scheme, tristate gates are utilized to implement the mode switches for test and work, and convert some registers in DSP data path into scan chains and cut off feedback loops in DSP data path during testing. This scheme has advantages such as good generality, good testability, and low additional hardware overhead without degradation of performance for original VLSI.2. In accumulator-based BIST environment, TP generation for DSP data path is discussed. It is proved that 2n-bit TP for n-bit adder and subtracter can be synthesized by vectors from two n-bit accumulators. Regarding details of adder and subtracter in DSP data path, an optimized method for the TP generation based on accumulator is explored through optimizing the lowest significant subspace of the TP. Results of simulation experiments show that the optimaized TP cover combinational stuck-at faults of adder completely. TP of array multiplier are studied and it is proved that accumulator can generate them too. Simulation results show that the TP can cover all single and double combinational stuck-at faults of array multiplier. At the same time, TP of constant input multiplier are discussed and it is pointed out that accumulator can generate them.3. TP generated by accumulators are studied and an effective method to generate TP for low power consumption testing of DSP data path in accumulator-based BIST environment is presented. Basic idea of the method is that encoded the TP produced by accumulation generator into Pseudo Gray Code to reduce the overall switching activities of the circuit module during testing. This code can be implemented economically by reusing the adder in DSP data path. Simulation results show that the encoded TP could greatly decrease test power consumption in accumulatior-based BIST environment.4. A method for testing in order and layer is researched for DSP data path in the environment of BIST based on accumulator. For this method, some adders in DSP data path are reused as generators of its TP and some registers in data path as scan chains. According to the regularity of DSP data path architecture, testing of DSP data path is performed in order and layer. This approach has advantages such as good generality, high efficiency, short testing duration, high fault coverage and low consumption for additional hardware.5. Adder test based on accumulaor generation is researched and an effective way is presented for the self-test of adders in DSP data path. Mind of accumulator-based compression of test response is extended, and then a BIST scheme for adders is proposed. According to the schemes, the concept designs are carried out for the self-test and BIST of ripple carry adder, respectively. Simulation shows that the self-test and BIST indicated above has the advantages, such as high testing capability and low additional hardware overhead. These researches will be helpful to solve the critical self-test issues regarding accumulation-based generator and compressor of DSP data path in accumulator-based BIST environment.