Test Generation Based On Hiberarchy Model At Register Transfer Level

Design verification and test of Integrated Circuits (ICs) are necessary techniques to guarantee the validity of a digital system. Thereinto being a primary part of them, test generation gets broad attention. This dissertation firstly summarizes the theory and method of test and verification; secondly introduces some high level testing methods at Register Transfer Level (RTL); lastly designs a feasible RTL test generation method which can generate useful test sequences for function test or verification.The original ideas are explained as follow:1. Creating an effective RTL behavioral model.Based on the control structure and data path of circuits, a new two-level RTL model is represented, termed Control Flow Graph/Data Flow Graph (CFG/DFG). At the first level, the connection of statements is expressed by CFG; at the second level, the detail of a statement is expressed by its DFG. Thus the model realizes the hiberarchy-description of circuits, which benefits simple form, small size and facile operation comparing with other models. In a word, it not only can decrease the complexity and improve the efficiency according to practical situation, but also can be used in simulation, testing and verification universally.2. Defining a testability measure of statement.To execute statements rightly, Static Sequential Depth and Dynamic Sequential Depth are defined based on the function and execution sequence of statements. At the same time, the corresponding algorithms are presented respectively. Based on the testability measure, a performance of circuit can be reflected horizontally and vertically, which provides convenience for RTL test generation.3. Presenting a RTL ATPG algorithm based on testcase.Aimed at branch coverage, bit-function coverage and statement-observability coverage measures, a generation method of high level testcase is represented using CFG/DFG model. Though the method, a block of testcase can be generated by executing two sub-procedures alternately. Then using some input measure, test sequence of a certain length can be gotten, which realizes the testing wholly.