The Research On Reconfigurable SoC DFT Structure And TLB Test Scheduling Strategy

Advances in semiconductor process and design technology enable the design of complex system chips. Traditional IC design, in which every circuit is designed from standard-cell libraries, is more and more replaced by a design style based on embedding large reusable modules, the so-called IP cores. Resulting from the use of reusable IP cores, the design scale and function have changed from the previous application specific VLSI into the current SoC. However, a challenging problem comes along with the increasing in size, complexity, and shortened design cycle. The testing of SoC is now seen as a major bottleneck in the development of SoC.Due to the provision sources, circuit structures and design styles of the embedded IP cores vary greatly, the traditional test method is no longer qualified for the testing of SoC, hence the design-for-testability (DFT) for SoC is necessary to be introduced. Nowadays, the SoC test is mainly to employ the test pattern provided by different IP core vendors to accomplish the test for the embedded IP cores. Thus, the DFT hardware architectures including test access mechanism (TAM) and wrapper must be constructed. TAM transfers test data between primary input/outputs ports of SoC and IP cores, and the wrapper enables independent test of IP core. Meanwhile, the complete test scheduling strategy should be explored to further enhance the utilization ratio of SoC test resource and reduce the test overhead of SoC. The related study is just the focus in the international current research domain of SoC DFT, and the thesis of this paper is based on it.Through fully analyzing the IEEE Std 1500, popular SoC DFT structures and test scheduling strategies, this paper presents a novel two-level SoC DFT scheme which can be applied on the both SoC IP level and top level, and fixes on reconfigurable SoC DFT structure and two-level balance (TLB) test scheduling strategy as the research emphasis. The major contents and contributions of this paper are:A novel two-level SoC DFT scheme which can be applied on the both SoC IP level and top level is presented in this paper. The scheme overcomes the limitation that the traditional SoC DFT usually only focuses on the top level, and it's possible to further enhance the utilization ratio of SoC test resource and reduce SoC test time.A reconfigurable SoC DFT structure based on TAM channel (TC) frame is also proposed in this paper. This DFT structure sets the hardware frame of IEEE Std 1500 as reference.To achieve the reconfigurable SoC DFT structure, this paper abandons the conventional sub-TAM frame. This paper defines the complete specification about the essential components such as wrapper, TAM and test controller, and designs the cell circuit model and extended model of those key components. The mathematical model of test time of WSC and IP are also established.A novel mathematical model of SoC test cost is established. Aiming at the minimum SoC test cost, test scheduling strategy is considered from test area overhead and test time. The limitation that traditional test scheduling usually only targets at SoC test time TSoC is broke and the pure theoretical work that adding test area to reduce test time is avoided.This paper creates TLB test scheduling strategies which can be applied on the both SoC IP level and top level, respectively, and founds the corresponding integer-programming model and heuristic algorithm. These mathematical models and algorithms not only increase the utilization ratio of SoC test resource and reduce SoC test time on the arithmetic level, but also obtain the final important hardware-design parameters which determine the reconfigurable SoC DFT structure. These works break not only the limitation that the traditional SoC DFT usually only focuses on the top level, but also that conventional test scheduling strategies only optimize test objectives on pure arithmetic level.This paper verifies the algorithm, realizability and reusability of TLB test scheduling strategy. These verifications are based on ITC'02 SoC benchmark circuits; therefore, the verification results are of some reference value.Through the comparison and analysis of the verification result of several classical references of this research domain, it can draw a conclusion that the two-level SoC DFT scheme has the advantages of increasing utilization ratio of SoC test resource and reducing SoC test time. The average percent of utilization ratio of SoC test resource can be enhanced from 10.85% to 24.13%. The average SoC test time can be reduced from 6.11% to 15.26%. Meanwhile, the two-level SoC DFT scheme has an 89.16% utilization ratio of SoC test resource.In international current research domain of SoC DFT, the IEEE Std 1500 defined in August 2005 is just a frame standard and needs to be further consummated. Therefore, the research production of this paper is of some relative reference significance for the further work of the IEEE Std 1500. Meantime, it also has theoretical significance for the SoC design and EDA tool design.