register transfer level - Globe Thesis

Keyword [register transfer level] Result: 1 - 20 \| Page: 1 of 2
1.	Research On RTL Fault Models And Test Generation
2.	Test Generation Based On Behavioral Model At RT-level And Delay Testing
3.	SOC Design For GSM Handset Baseband Processing
4.	Test Generation For Integrated Circuits At Register Transfer Level
5.	Test Generation Based On Hiberarchy Model At Register Transfer Level
6.	2-D DCT/IDCT IP Core Design And Implement Using FPGA Technology
7.	Design And Implementation Of USB SIE IP Core
8.	Register Transfer Level Coverage-Driven Verification Of External Memory Interface
9.	Research And Design Of AES Encryption Soft IP Core
10.	Design And Research Of Discrete Cosine Transform IP Croe
11.	A Study On A Test Method Of Internal Functional Modules Generating Test Vectors For RTL Data Path
12.	Research On The Error Detection Method Via Static Analysis Of RTL Designs
13.	Research On Low Cost Test Method For RTL Data Path Under Power Constraints
14.	Digital Signal Processing On Wireless Communication Oriented Microprocessor Design
15.	Research On High-Level Equivalence Checking For SoC Designs
16.	Pond IDE: Machine level program development environment and register transfer level simulator for a massively parallel computer architecture
17.	System-on-a-Chip (SoC) based hardware acceleration in Register Transfer Level (RTL) design
18.	Power optimization from register transfer level to transistor level in deeply scaled CMOS technology
19.	Register-transfer-level design verification: Coverage and acceleration
20.	Transparency-based hierarchical testability analysis and test generation for register transfer level designs
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