High Speed Low Power Research And Design Of Adc

As a new wireless communication technology, Ultra Wideband (UWB) has several advantages such as high speed, low power, high immunity to interference and good security. Therefore it has become a hot issue in wireless communication field. A complete UWB system includes two digital basebands, one Radio Frequency (RF) transmitter, one RF receiver, one digital-to-analog converter (DAC) and one analog-to-digital converter (ADC). In order to meet the bandwidth requirement of the system and be competitive in the prosperous mobile terminal market, the ADC should has high sampling rate while maintain a low power consumption. The Chinese national UWB standard uses dual-carrier orthogonal frequency-division multiplexing,(DC-OFDM), which generates2banks of I/Q signals due to two carriers. So the total number of ADC is four.Based on the above research background, the main contribution of this thesis is:(1)Design a four-channel8bit264MS/s folding and interpolating ADC compatible to the national standard. Four sub-ADCs are integrated on one chip so as to simplify the testing system. Sub-ADC adopts the architecture of folding and interpolating which can reduce the number of comparators; single front-end track and hold(T/H) circuit helps mitigate the impact of clock skew; the buffer stage isolates the substrate capacitor from the output node, improving linearity; cascaded folding is used to reduce power consumption and makes a larger gain of the signal path; inter-stage pipelined switches are added to loosen amplifiers’ settling requirement; active interpolating can further increase gain and lower the input-referred offset of comparators.The ADC in fabricated in SMIC0.13-um,1.2-V/2.5-V, single-poly, eight-metal mixed-signal CMOS technology. The core area is2.46mm2and total power is140mW. When data are truncated to6bit, one sub-ADC can achieve33.7dB SNDR and42.1dB SFDR at2.3MHz input. While it demonstrates31.4dB SNDR and36.7dB SFDR at Nyquist input. A complete test shows that the performance deviation between each sub-ADC is within5%. Finally the whole system test verifies that the ADC can meet the standard.(2)In order to further reduce power, after analyzing and comparing the current low power architectures, an improved binary-search (BS) scheme is proposed. It utilizes two time-interleaved capacitor arrays to shift the input signal, which fixes the reference voltage in each comparator. Compared with aforementioned folding and interpolating, power consumption is cut by a huge amount; while compared with current BS schemes, it not only reduces number of comparators but also avoids complicated switch network. If comparators with built-in threshold are used, resistor ladder can be further discarded. As a result, there’s no static power in the ADC.The spec is6bit500MS/s. Simulink model is established and simulation result shows that the new scheme works well and can advance into detail circuit design.