Functional Verification Of YHFT-DX High Performance DSP

With the rapid development of scale of chip design, how to effectively verify theentire chip has gradually become the bottleneck of the products to market quickly.Relevant Data has shown that, verification has occupied for more than70%of the entiredesign cycle, as a result, it has become a problem of urgent need to solve that how toimprove verification efficiency, reduce the workload of the verification staff, andimprove the verification process.Large scale digital integrated circuit verification techniques mainly include:simulation verification, FPGA emulation and formal verification. How to make rationaluse of various verification techniques to improve verification efficiency, has a veryimportant practical significance to the chip design. The main research of this topic is asfollows:1. CPU core of the YHFT-DX chip is used to research functional verificationtechnologies based on simulation verification. According to the special structure of thechip, simulation platform is set up, test stimulus for simulation verification is generated.In addition, this paper takes YHFT-DX Testchip for example, makes relevant researchon post simulation.2. The research of the FPGA emulation, which includes code conversion fromASIC design to FPGA design, the design of platform of FPGA emulation and so on, isdone on the two data paths of the YHFT-DX Testchip.3. The research of formal verification based on equivalence checking is done onthe example of YHFT-DX chip, using the software tool of Formality of the SynopsysCompany. The problems of tri-state gate, gated clock and so on in the designoptimization process is studied, and corresponding solutions is put forward, andfunctional verification of CPU core, load/store unit, conditional register and register filein YHDT-DX chip has been accomplished.4. This topic has done some testing on function, frequency, clock, scan chain andother aspects of the YHFT-DX Testchip after tapeout.