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Functional And Timing Verification Of Image Process Engine Of Video Format Convert Chip

Posted on:2013-09-25Degree:MasterType:Thesis
Country:ChinaCandidate:X ChenFull Text:PDF
GTID:2248330362461774Subject:Microelectronics and Solid State Electronics
Abstract/Summary:PDF Full Text Request
With the development of semiconductor manufacturing and IC design technology, the IC is becoming more and more complex driven by Moore’s law, and the time of VLSI and ULSI has been turned on. The following problems which are the bottlenecks of IC R&D are functional verification and timing verification. Functional verification, which means to verify whether the design achieves the specifications, has accounted for 60%~70% design resources. Timing verification means checking the inner delays of chips to verify that whether it meets the constraints.Based on the research of“Video Format Convert Chip (VFC) Development”which is funded and initiated by Tianjin Science and Technology Committee, the thesis puts its focus on the timing verification and functional verification of Image Process Engine (IPE). First of all, the Staitic Timing Analysis (STA) of IPE was made with PT, and the reports show that the design can work normally under the specified clocks, and there are also some certain margins. After introducing the architecture of VFC and IPE briefly, a detailed verification plan was made. By using Constrained Random Test (CRT) and Coverage Convergence Technology (CCT) as a guidance, a verification method of chips based on resembling directed test was proposed to solve the problem of how to cover all the functional points quickly and speed up the verification progress. Then the thesis specifies the process of weight correction in resembling directed test which is used in test-bench. At last, a hierarchical architecture of test-bench which is recommended by VMM is used for the functional verification of IPE on the scenario layer.The simulation data and experimental results show that the test-bench driven by functional coverage can make a good join of stimulus vectors generation and result checking, and verify the IPE automatically and efficiently by using the resembling directed test. From the visual effects, the IPE converts different video formats successfully. And the IPE achieves the goal of putting complex algorithms such as scaling and flesh tone correction into one chip.
Keywords/Search Tags:Functional verification, Static Timing Analysis, Constrained Random Test, Resembling directed test, VMM
PDF Full Text Request
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