The Verification And Optimizationof BSU Arithmetic Unit Of X-DSP

With the increase of the IC scale and the shrink of the design period, the requirements for the function verification become more sophisticated. Whether the designers can operate full function verification in the regulated time has played a vital part in marketing in time of the IC products. The relative data shows that the efforts on RTL code verification have reached 70% of that of the whole design, being a crucial step of the IC design. Therefore it needs to improve the verification procedure and reduce the workload of the verification engineers so that it can elevate the verification efficiency.The X-DSP Chip is an independently developed highly advanced 32-bit DSP whose core BSU can implement multi-functional fixed-point operation and floating-point operation. This paper does thorough research on the BSU function, verifies the instruction plus the unit function and also optimizes the timing of the design. The main contents of this paper are as follows:1. It introduces the X-DSP chip’s entire architecture and data path. It also explains the detailed function of every instruction based on classification of the BSU instructions and the related working principle of the control register.2. Applying the BSU of the X-DSP chip as an example, this paper discusses the verification technique based on simulation. It generates verification excitation profiles based on the characteristics of the BSU instructions and exception operation function. It also analyzes the code coverage rate of the simulating verification and make it meet the requirements.3. Using BSU of the X-DSP chip as an example, this paper works on formalverification techniques based on equivalence checking method. The software adopted in this research is ATEC and it accomplishes the whole BSU instruction verification and reaches 100% code coverage.4. It optimizes the timing of the BSU module and eliminates the key timing-violating path so that it accelerates the units’ operating speed, meeting the design’s performance requirements.At last, combining simulating verification with equivalence checking method, this paper executes full verification and optimizes the timing of the BSU module via which it finally meets all the requirements of the design specifications.