Verification On Chip For Ultrasonic Heatmeter ASIC

To meet the requirement of sustainable development, energy saving problem is becoming the hot issue in scientific research. More and more heatmeters are now being used in heating systems, which can measure the heat consumption in these systems. Most of the traditional heatmeters in our country is mechanical ones and have many problems with themselves. To overcome the defects of mechanical heatmeters, ultrasonic heatmeters are developed.Ultrasonic heatmeters have many advantages such as:very high accuracy, easy to use and convenience for digital management. Recently, with the development of electronic techniques and the decrease of electronic elements prices, manufacturing cost of ultrasonic heatmeters has declined dramatically. In order to develop ultrasonic heatmeters of our own intellectual property, this thesis dose a systematic study on the core part of this system——the time-to-digital converter.First of all, this thesis gives an introduction to the methods and steps in ASIC design. After reviewing theoretical basis of TDC design, an IP core architecture with dual measurement model is proposed. Secondly, the TDC model is divided to some sub-models:the high speed unit, the controller, the clock unit and the post-processing unit. And in the end, considering the low success rate in IC design, this thesis discusses the necessity for verification and does a systematic study to the methodologies in verification. Comprehensive verification is done to the design using methods such as: FPGA based function verification, PT based timing verification and Formality based formal verification.The Top-Down design methodology and RTL-level Verilog HDL are adopted in this thesis. Based on Xilinx ISE integrated environment, input and functional simulation are completed. Simulation verification is done with Modelsim from Mentor Graphics Inc. and FPGA function verification is done with Basys board from Digient. Then, static timing analysis is completed to the gate-level-netlist after synthesis to see whether there are some cases timing is not satisfied. In the end, we did equivalence verification to RTL level code and gate-level-netlist to verify the equivalence between RTL code and gate-level-netlist after logic synthesis. The main merits of the paper are as follow:a complete design solution is provided and the verification from RTL to gate-level-netlist after synthesis is achieved. According to the problems in logic and time sequence, feedback is added to the model, which can solve the functional and sequential problems before placement and routing.