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Usb-otg Chip Design And Verification Of Systemc Transaction-level,

Posted on:2006-01-16Degree:MasterType:Thesis
Country:ChinaCandidate:G Z YangFull Text:PDF
GTID:2208360152997955Subject:Circuits and Systems
Abstract/Summary:PDF Full Text Request
USB-OTG, the technique developed in recent years, realizes the data communication between USB devices. It mainly applies to connection and data exchange between all kinds of devices or mobile devices, especially PDA, mobile phone and consumption electronical devices. It not only conveniences the direct connection between the devices including digital camera, vidicon, printer and so on, but also realizes the data exchange between 7 different memory cards. According to the USB-OTG features and market demand, we planned for researching and developing the chip of USB-OTG. In the process of the USB-OTG chip design, I participated in the front design of the chip's digital part, trying the method of SystemC transaction level on the system function verification platform. This paper finished the goals as follows: 1. Understood the design flow of digital chip and learned to use the tools of Synopsys and Cadence platform. 2. Analyzed the principle of USB2.0 protocol and the implemented OTG protocol. 3. Defined the system architecture of USB-OTG chip by referring to the existing USB chip architecture. 4. Coded the RTL Verilog HDL of USB-OTG and simulated the timing of submodules. 5. Set up the verification platform based on SystemC and verified the system function of the chip. 6. Synthesized the chip by Design Compiler and passed the check of Static Timing Analysis by PrimeTime(PT). After front-end design and verification, the RTL codes of USB-OTG passed the practical verification on the FPGA of Xilinx Spartan2e XC2S300E, realizing the host function and the peripheral function of USB-OTG. The verified RTL codes provide the exact function netlist for layout.
Keywords/Search Tags:USB, On-The-Go, OTG, SystemC, transaction level verification, Design Compiler(DC) Synthesis, PrimeTime(PT) Static Timing Analysis, front-end, back-end, netlist
PDF Full Text Request
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