Research And Design Of The 14bit 40MSPS Pipelined ADC

Continuous improvement of modern society and the rapid development of silicon integrated circuits making the application of electronic products more and more widely. As people’s growing demands for electronic products, electronic products play an increasingly important role in daily life, which promotes the rapid development of electronic technology. On the one hand the signals in nature that people can see and hear are in analog state, which need to be convert into digital state to facilitate the processing, transmission, and analysis. On the other hand, digital signal processing technology and communication technology are extensively used in various fields,such as medical, commercial, military, etc. So that the digitized degree of high-tech fields is deepening, and the electronics industry has already formed the structure of the digital technology as the core. High performance ADC and DAC as indispensable bridges between the analog domain and digital domain have become a key part of modern electronic technology research. Domestic demands for analog-digital converters continued to increase from 2007 to 2015, and will continue to maintain the growth rate.The article begins with the comparision of various types of analog-to-digital converter, in the end the pipelined ADC with advantages of conversion speed, high precision while lower power consumption, becomes the preferred structural design.The paper describes the implementation of a 40-MS/s 14-bit pipelined analog-to-digital converter(ADC) in 0.18μm CMOS technology. The pipeline architecture consists of a series of 2.5bit stages, one stage 2-bit flash ADC and a time align & digital error correction circuit to get the final output digital codes.In the structure, the traditional pipelined analog-to-digital converter is optimized to improve the performance of ADC. Pairs of non overlapping clock are generated by two non-overlapping clock generation circuit. The two main non overlapping clocks only applied respectively to control the sample-and-hold state of the odd and evenstages, which can reduce the influence of capacitive load for the key clocks, and the additional two non-overlapping clocks are responsible for bottom plate sampling by controlled the bootstrap switch in MDAC. The basic building blocks of Pipelined ADC is 2.5 bit quantization units which composed of Sub ADC, Sub DAC and residue amplifier. The most important module in the sub ADC design is the comparator array. In the paper, the use of the structure of dynamic comparators not only ensures the speed of the comparision, but also reduces the power consumption of the whole circuit greatly. In addition, the bootstrapped switch technique in the MDAC circuits that is composed of sub DAC and residue amplifier can reduce the switch conduction resistance and the induced nonlinear distortion by charge injection effect and the clock feed through. It ensures the authenticity of the sampled signal. As the key circuits of MDAC, the operational amplifier in this design adopted the gain-boosting amplifier structure which achieves the gain of 124.8dB and the GBW of1.005 GHz. The operational amplifier meet requirements of the analog to digital converter well.The ADC design is provided with a 3.3V power supply, and the total power dissipation is 100 mW in typical case. In the layout design, taking into account the capacitor mismatch error, switch resistance error and the like, extracting parasitic resistance and capacitance parameters, the ADC achieves a SNDR(signal-to-noise-and-distortion ratio) of 82.4dB and ENOB of 12.6bits ultimately at40 MHz sample rate with a sine wave input of 17 MHz frequency. The entire ADC chip occupies 2.2mm×1mm area. The ADC in this design meets the requirement well.